Examining the pitfalls of this popular option
It makes for easier routing, reduced area and can also reduce parasitics. So if it is possible to do so in layout, engineers often take the opportunity to share two or more MOS devices. But is this always beneficial?
While there’s no doubt that sharing devices offers the physical designer some significant advantages in layout, it is not without risk.
The very nature of sharing two or more devices changes their characteristics. This potentially makes them prone to processing artefacts that wouldn’t otherwise have any impact.
Take STI stress (Length Of Diffusion effect). Sharing two or more devices will change their SA and SB parameters, impacting Id (drain current). Schematic simulations do not account for this impact and can only be seen if SA and SB parameters are extracted and simulated post-layout.
The time and cost needed to extract and simulate every single layout to account for this effect means sharing may not always be feasible. STI stress also means that the circuit’s functionality is not known until after the layout is complete. This creates a scheduling risk – designs may have to be altered post-simulation, not because of interconnect parasitics but because of differences in device parameters between layout and schematic.
Sharing doesn’t just impact STI stress. It can also make devices prone to mismatch due to mask shift, mask misalignment, implant shadowing and numerous other processing artefacts. Through judicious use of dummy devices, some or all of these artefacts can be “designed out” in the layout. But had they not been shared in the first place, it’s likely that the devices would not be have been prone to these effects.
So when deciding whether or not devices can be shared, it’s important to first understand the impact on a device’s characteristics, and to accept and manage the risk of functionality changing pre- and post-layout.