– NANOMETER
Sometimes, what should be the simplest, most seemingly innocuous design decisions, are actually the ones that impact layout and silicon the most, be it from an effort point of view, increased area, reduced yield, reduced latch-up immunity or a host of other issues. IC Mask Design’s Nanometer Layout course sets out to look at the common design and layout practices applied today and analyses how applicable these techniques are, as technologies continue to shrink.
The Nanometer layout course helps center layout techniques on a specific node and provides practical real-life solutions to the challenges the layout and design engineer will experience when transitioning between nodes.
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PRICE OF COURSE
POA
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DURATION OF COURSE
4 Days
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LEVEL OF COURSE
The course expects the participants to already be very competent, confident, and comfortable with Analog layout, and ideally, they will have completed multiple different tapeouts on different technology nodes across numerous different applications.
Courses are delivered in a classroom setting and are designed to make sure there is lots of interaction between the trainer and you the attendee.
COURSE SYLLABUS
Please contact us for more information on the the course syllabus
