– CASE STUDY 4

There are a myriad of increasingly complex design issues that most be overcome
at FinFET nodes.

Understanding the implications in layout in areas such the grid pattering, standardization of row heights, the limiting set of FinFET lengths and multi-pattern based metal grids is essential. Layout at these nodes is critical with the engineer requiring an awareness of the design and what the functional design engineer is trying to achieve. IC Mask Design has been completing layout designs on 16nm since 2014, 7nm since 2017 and started working on 5nm in 2018. We understand the challenges that customers are facing at these nodes and our focus on quality reduces the risk of costly respins.