– FinFET Layout
Sometimes, what should be the simplest design decisions, are the ones that impact layout and silicon the most. Never is this more pronounced than when working on small geometry nodes or when transitioning between nodes, particularly when transitioning to a FinFET technology.
IC Mask Design’s FinFET course takes an in-depth look at the key challenges involved in the layout of high precision and high-speed analog designs on 16nm technology nodes and below.
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PRICE OF COURSE
POA
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DURATION OF COURSE
2 Days (4 half days on-line)
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LEVEL OF COURSE
The course is designed for Designer Engineers, Layout Engineers, CAD Engineers, and Software Engineers.
Courses are delivered in a classroom setting and are designed to make sure there is lots of interaction between the trainer and you, the attendee.
COURSE SYLLABUS
Please contact us for more information on the course syllabus
