– FinFET (≤16nm)

Each technology node aimed to reduce the minimum gate length of a device, bringing with it improvements in speed and area, but at the cost of manufacturing expense & complexities, and other issues such as leakage. FinFET manufacturing diverged completely from previous planar solutions, where the poly gate wrapped around the channel on all 3 sides.

This new 3D structure required extremely homogenous patterns in layout, which required the foundries to introduce many more design rules and restrictions, enforcing uniformity in layout. Working to fixed pitches (poly and metal), new devices with fin counts instead of channel width and challenges around dummy/tuck poly over oxide edges required a complete shift in mindset and layout/design methodologies.
Whilst some larger technologies saw some limited multipatterning, FinFET was also the first one to avail of it consistently, requiring the layout and designers to address the challenge of colouring in layout.
IC Mask Design has been completing layout designs on 16nm since 2014, 7nm since 2017 and started working on 5nm in 2018. We understand the challenges that customers are facing at these nodes and our focus on quality reduces the risk of costly respins


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