Why low-risk design depends on a clear understanding of MOS parameters
Apart from device type and subtype, and actual connectivity, MOS devices have 4 key parameters that describe their operation and characteristics: channel width (W), channel length (L), number of fingers (NF) and multiplicity (M). (While some PDKs define W as finger width and others use it to refer to total width, for clarity I will define W as finger width in this article.
Channel length is always a fixed parameter. But both schematic and layout designers often use W, NF and M interchangeably. As long as the overall total effective width is the same between layout and schematic, this is often considered to be OK.
Not all parameters are equal
But is it? There are fundamental differences between these three parameters, all of which can potentially impact the silicon’s functionality. Understanding these differences is key to reducing risk.
Take number of fingers. A device with a finger width of 12μ and just 1 finger is not the same as a device with a finger width of 6μ and 2 fingers. They may be logically equivalent but there are important differences between them, because the act of folding the device changes its characteristics significantly and in different ways.
First, in the example above, there is now an asymmetry between source and drain that was not there previously, meaning that one terminal will have less than half the capacitance of the other. Current distribution through the device also changes, as do other parameters like gate resistance, and SA and SB STI parameters.
The all-important link between schematic and layout
These changes may or may not impact the functionality or performance of the circuit, but by using W and NF interchangeably, we fundamentally break the direct link between schematic and layout. Only a full device parameter extraction of the layout, together with simulation, will prove that functionality or performance have not been altered in a detrimental way.
Similarly, multiplicity (M) assumes that the device is made up of individual islands of diffusion with no sharing. By sharing them, the layout engineer changes the actual characteristics of the devices, potentially introducing risk into the design.
The lowest-risk approach is to maintain a 1:1 relationship between schematic and layout, with layout engineers strictly adhering to the parameters defined in the schematic and design engineers ensuring they understand the subtle differences between the parameters.
This topic is covered in greater detail in IC Mask Design’s Advanced Analog Layout course. For more information please click here: https://icmaskdesign.com/advanced-analog/
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