Speaker Bio:
As Technical Lead at IC Mask Design, Gaurav works with an exceptional team of skilled Layout Engineers, delivering high-quality layout solutions for various projects across different foundries and nodes. Gaurav has over 8 years of experience in physical implementation, specializing in Analog, RF, and mixed-signal integrated circuits.
Brief Summary of Presentation:
Parasitic extraction is crucial for ensuring layout adherence to specifications, but it often causes delays and potential redesigns. To address this, a dynamic approach has been proposed, integrating resistance and capacitance values into Width Spacing Patterns (WSPs) for real-time parasitic extraction during the wiring process. This technique offers early and accurate parasitic estimation, improving layout quality from the start and facilitating better schematic-to-layout translation. Overall, this approach saves time and effort throughout the layout life cycle, reducing the need for significant changes after post-layout parasitic extraction.
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