– Metal Gate Processes (≤45nm)

The transition from polysilicon to metal gates was a seismic step in semiconductor manufacturing bringing with it many challenges around polysilicon density and spacing to neighbouring poly another modeled proximity effect impacted by layout.

In order to accurately manufacture polysilicon gates, especially at minimum length, whilst maintaining a small CDV (critical dimension variance), rules around orientation of polysilicon, polysilicon min and max area restrictions (locally and globally) as well as rules relating to density gradients were all introduced, presenting new challenges to layout and design.
These nodes also carried forward the challenges of previous/larger node, and it was here that layout and circuit merged. A circuit design was never complete until the layout was done.
Understanding these challenges is key but having methodologies to allow you design out these issues or identify problems at a layout stage is where IC Mask Design’s experience pays off. Layout/design cycle times are not impacted and more importantly expensive spins of silicon due to unforeseen layout issues can be avoided.


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