CMOS technology asserts that for every
PMOS device sourcing a current, there is a complimentary NMOS device, sinking that same current.
As such, CMOS layout engineers are very au fait with laying out these devices in the same circuit, using a combination of engineering experience, and verification
tools (LVS, DRC, ERC and PEX) to ensure the circuit is manufacturable and is functionally equivalent to the schematic.
However, where the verification tools often fall down, is in detecting and warning of the many parasitic/unwanted devices and circuits that are formed when the intentional devices are laid out.
Taking the simple PMOS and NMOS layout above, we can see that it also creates two vertical PNP and two lateral NPN bipolar transistors, connected to each other.
These are connected in a shared base/collector formation, forming a positive feedback loop, where the collector of the NPN is also the base of the PNP (N-well), and the collector of the PNP is also the base of the NPN (P-Well).
On further examination of the circuit in this cross section, we can see that both the PNP devices share the same collector and the same base, except for a small resistive difference between them, which is negligible. Similarly, both NPN devices also share the same base and same collector, again assuming the small resistive difference between them is negligible. This allows us to simplify the schematic combing devices into a single bipolar symbol, with two emitter terminals. One emitter (the source) is hard connected to either power or ground, and the other emitter (the drain) will be at any potential between either power or ground.
In the case where the MOS devices are turned on fully, shorting source to drain through the channel, then the drain emitter and source emitter are at the same potential and are in parallel, effectively doubling the emitter area of the respective bipolar transistors, forming the traditional SCR (silicon-controlled rectifier) schematic, also referred to as a
thyristor.
This is a well-known and well documented circuit, that is the root cause of a failure mechanism called Latch-up. For either of the bipolar devices to turn on, there must be a Vbe voltage, where simplistically the emitter is at a different potential to the base.
Were they shorted directly to each other, the devices could never switch on, but in this case, they are connected to each other through the well resistance. Given a high enough resistance value and/or a sufficiently high amount of current flowing through the well across the resistance, an IR drop can be induced across the resistor, causing a potential
difference between base and emitter, switching on the bipolar transistor.
A single bipolar would only need to be turned on a small amount, leaking current into the well/base of the complimentary bipolar, causing that one to switch on more, which in turn would draw more current across the base/well of the other transistors, eventually causing both devices to switch on fully, creating a high current, low ohmic short between power and ground – i.e., the circuit latches up.
There are many different techniques for improving latch-up immunity in layout, but one common one applied in analog layout, is to increase the separation between NMOS and PMOS devices. This reduces the β (beta) of the lateral NPN by increasing the base thickness of the device, reducing the quality of the device and its ability to turn on.
Generally, the very nature of analog layout means that PMOS devices are grouped together into common wells, with a single, or low number of lateral NPN junctions to adjacent NMOS devices, where the spacing between them (β of NPN) is non minimum. This leads to naturally high latch-up immunity in most core analog circuits.
Digital layout on the other hand, is in stark contrast to this, with multiple N-wells (all connected in parallel due to being tied to the same supply), in close proximity, often minimum distance, to NMOS devices, creating multiple high β NPN junctions, making digital layout actually inherently risky to latching up.
Adding Risk To Analog
One of the most common features seen in analog design (and layout) today, is the use of pull-up and pull-down devices in a design, to power down circuits, reducing power consumption and leakage. These are usually small length/width complimentary switches, both NMOS and PMOS on the gates of current mirrors, which when turned on, disable the functional circuit. When turned off, the circuit operates normally, and the switches have no functional impact on the circuit itself. Given that they are a PMOS and NMOS pair, an inverter is needed to ensure both devices are switched on simultaneously.
Functionally, these inverters and switches are an “I don’t care” consideration in design, and often the circuit designer will select an inverter from a logic library, which is laid out using minimum rules and spacing, and likely use minimum size geometries for the switches. These seemingly innocuous design decisions can actually have many unintended harmful impacts in layout and silicon, from not availing of opportunity to improve matching (switches could be sized same as matched devices and used as dummies), to introducing potential patterning marginalities and DFM issues by incorporating minimum rule geometries and spacing into a non-homogeneous area of patterning.
Another potential concern is that of reducing latch-up immunity, because of the likelihood that the layout engineer will share the N-well of the inverter with the N-well of the PMOS devices already in the layout.
By doing so, they effectively by-pass the large spacing between NMOS and PMOS and create a high β junction, increasing the risk of latch-up in the circuit at that point. Whilst from a design perspective, these devices are an “I don’t care”, every decision in layout has an electrical consequence (not always a functional one) and an impact on manufacturability.
There are many solutions to avoiding this situation: Instead of using an inverter in the design, it can be created as separate NMOS and PMOS devices, placed far apart, keeping the β low. Alternatively, an inverter laid out using larger separation between PMOS and NMOS, with perhaps well contacts between them, could be used instead.
Ultimately though, it comes down to experience, knowledge and awareness of junctions and risk areas in layout and reducing risk in silicon should always be a primary concern.
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