A “multiple stamp” in layout is where a single well (P-Well or N-Well) has two or more separate well connections, which are not connected to each other through metal. The well connections are resistively shorted to each other, through the well itself.
Multiple stamps are often considered bad practice in layout and flagged by tools like ERC and/or LVS, but they don’t actually pose any risk in silicon. That said, whilst they may not pose any risk, they also serve no beneficial purpose, and for that reason, should be avoided.
A “soft connect” is a type of multiple stamp, where one or more of the well connections are tied to a device and/or supply rail. These are inherently risky, as they will induce current flow through the well, which is a condition that should be avoided at all costs, with the exception perhaps, of well resistors.
CMOS devices form parasitic bipolar devices, which when placed in close proximity to each other, create actual circuits, like an SCR (silicon-controlled rectifier – also referred to as a thermistor), which if triggered, can cause failure conditions such as latch-up.
The SCR has a shared base/collector junction between the vertical PNP (P+ diffusion, N-Well, P-Substrate) of the PMOS transistor and the lateral NPN (N+ diffusion, P-Well, N-Well) formed by placing an NMOS in close proximity to the N-well, where the NMOS is placed. The N-well acts as both the base of the PNP transistor and the collector of the NPN.
The SCR is a closed loop system, applying positive feedback, such that one device can cause the other to switch on a little more, which in turn switches the first device on a little more, and so on.
Latch-up occurs, when both devices are fully switched on, where the SCR holds the voltage stable, whilst sinking a large amount of current, creating a low ohmic connection (i.e. short) between power and ground.
In order for either of the of the bipolars to switch on, there needs to be a Vbe (a potential difference between the devices emitter and base). If these were directly shorted in metal, then the device would remain off. However, the base and emitter of both bipolars are connected to each other through the resistance of the well, and not through metal.
To avoid an IR drop across a well resistor, which would lead to a Vbe, causing the device to switch on, efforts are often made in layout to reduce the value of this resistance, by placing well contacts close to the base/emitter junctions of the bipolars.
Another way to avoid this switching on, is to reduce the current in a well. In fact, with the exception of well resistors, wells should not carry any current, even though inevitably there will be some stray current caused by factors such as capacitive coupling and so on. It is for this reason that soft connections carry so much risk, in that they can be a source of stray current in a well, which can in turn trigger latch-up conditions.
Of course, a “simple” fix in layout, would be to short the well connections together in metal, likely satisfying LVS/ERC checks and eliminating this risk. Or does it? The answer is “No”. Verification tools may no longer flag a soft connection, but this does not guarantee, that current will not flow through the well.
Shorting Source to Bulk – Design Decision
On a bulk CMOS process, both the source and drain of a MOS device (in this example an NMOS) are inherent P/N junctions (diodes), where the N+ diffusion is the cathode and the P-Well is the anode.
Diodes are also capacitors, where the anode and cathode are the conductors and the depletion region between them, acts as the insulator.
The thickness of the depletion region is dependent on both the polarity of the voltages on the anode/cathode and the potential difference between them. In design, there is an effect called the “Body Effect”, caused by having a capacitance on the source of a MOS, which impacts the VT (threshold voltage) of the transistor.
One common way of eliminating this effect is by shorting the transistors source to its bulk, effectively shorting both sides of the diode/capacitor together. But is this always a good idea? Does this seemingly innocuous design decision introduce any risk into silicon in terms of introducing current into wells, or reducing immunity to latch-up?
The answer is “yes” – shorting a devices source to its bulk, reduces latch-up immunity, as now both the well (bulk) and the source act as a supply for that device, and all supplies carry current.
This is best explained in the example below. Here we have 4 NMOS devices, all with their own P-Well connection in close proximity to them. All 4 devices are shorted in metal to their own well connection. Underneath the devices is a wide, low ohmic supply (ground), which also runs over another P-Well connection. Devices A, B & C are then shorted from their bulks to this low ohmic supply rail, where device D is not. In addition, there is a second, narrower and longer supply rail above the blocks, which is going to another block.
This is clearly bad layout, and in this case LVS/ERC would flag a soft connection for device D, due to the well connection, not being connected in metal to any other of the well connections in the same well. If/when device D switches on, it would draw current from the supply rail (combined with the well connection), and through the well.
A simple fix to this would be to short the well connection of device D, to the supply through metal, removing the soft connect and eliminating the ERC error. However, what ERC or LVS does not check for, is how or where this connection is made. Once the well does not contain multiple stamps and is not soft connected, then it will pass the checks. In the “fixed” example below the shared bulk/source connection for device D is connected in metal to the narrower/longer higher ohmic rail above, instead of the lower ohmic rail below. But does this eliminate the risk of current through the well?
The short answer is “No”. In this case when device D switches on and looks to source/sink current from the supply rail, the current has two different paths that it can take – we have effectively created a current divider.
It can flow through the longer, narrower, higher ohmic metal (blue resistor), or through the well (red resistor), between the bulk connection of the device itself and the bulk connection underneath the main supply rail.
How much current (if any) flows through either of the resistors, will depend on their values. Ultimately though, the design decision to short the bulk to the source, promotes the well to being a potential source of supply, and poor implementation of that connection in layout, albeit one that passes verification checks, can result in stray current flowing through wells, introducing additional risk of latch-up.
Separating Source from Bulk
The simplest way of reducing this sort of risk is to separate the source from the bulk.Now the supply will always draw/sink current from the source, and never through the well. Of course, these two nets must be shorted at some point, as they do need to be at the same potential. And as previously mentioned, by separating them, you do risk having a potential difference between them, causing a capacitance, which leads to a VT shift due to the body effect.
In this case, as shown in the example below, all well connections are connected to each other through metal, but none of them are tied locally to the supply. The sources of reach of the MOS devices are shorted to this supply, so when they switch on, the current path is always through metal, and can never be through the well, as that current path is no longer there.
The original design decision, shorting source to bulk, isn’t solely at fault here. Ultimately, it is poor quality implementation in layout, that introduces the risk. But the design decision allows for this poor quality implementation to exist. By separating the two nets, it is not possible to resistively couple current through the well, regardless of how the layout is implemented.
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