Congratulation to IC Mask Design Technical Lead, Gaurav Masiwal, who presented on “Real-time Parasitic Estimations using Width Spacing Patterns” at CadenceLive 2023 in Munich October 11th. A major challenge in the field of layout design lies in the post-layout parasitic extraction process, which often introduces delays and the potential for significant modifications in the layout. This paper introduces a novel approach to address this challenge, providing real-time parasitic estimations using Width Spacing Patterns (WSPs).
Traditionally, parasitic extraction occurs after a layout or multiple hierarchical layouts are completed, leading to potential delays in project timelines and even worse deterioration of the overall layout quality. Even minor adjustments can extend the process, sometimes requiring a complete redesign. To mitigate these issues and streamline the layout process, a dynamic solution is needed.
The proposed technique integrates parasitic resistance and capacitance values into WSPs, allowing real-time parasitic estimations during the wiring phase. This approach offers early and reasonably accurate estimation of parasitic effects specific to individual nets, resulting in higher-quality layouts from the start. It also enhances the translation of schematic specifications to the layout. Additionally, it provides compatibility with various metal layers embedded in WSPs, offering flexibility to meet diverse layout requirements.
One key advantage of this approach is its support for debugging through post-layout extractions. It provides a detailed breakdown of parasitic effects per metal layer, distinguishing between device and metal-added parasitics. This technique is seamlessly integrated with the CDT and PG-Pcell approach, ensuring compatibility with existing layout practices.
In conclusion, this innovative technique empowers layout engineers with real-time access to parasitic information. Not only does it enhance the initial quality of layouts, but it also reduces the likelihood of significant post-layout modifications. This leads to valuable time and effort savings throughout the entire layout life cycle, ultimately improving efficiency and the overall quality of the layout and schematics.
For those of you who missed the CadenceLIVE 2023 presentation IC Mask Design’s Gaurav Masiwal will be hosting a webinar “Real-Time Parasitic Estimations Using Width Spacing Patterns” on Oct 24th at 16:00 GMT/ 08:00 PST click here to register: Registration (gotowebinar.com)
Share this on...