BACKGROUND
VC-funded start up primarily focusing on novel design concepts for designing next-generation processors, which are smaller in area and consume less power
Requirements & Challenges
Requirements & Challenges- The customer had very limited internal layout resources and no experience of working on FinFET technology nodes
- For first ‘proof of concept’ silicon, customer had outsourced to a large VLSI services provider, but the layout produced had many design rule violations and did not deliver on expected area savings
- IC Mask Design was tasked with optimising the customer designs for FinFET layout, and developing a layout methodology that would allow for DRC clean silicon, efficient layout flow and ultimately provide a significant area saving over using manufacturer’s logic cells to deliver equivalent functionality
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Outcome
Outcome- Developed highly area-efficient logic tiles that were completely free of design rule violations (requiring no waivers from the foundry)
- Delivered area savings in excess of 20% on foundry provided logic cell equivalents
- The title methodology developed provided a working template for the customer’s own internal layout and design teams