Posts Categorized: Technical Articles

Drain and Source Area. How Do They Change With Device Folding?

August 31, 2022

Reducing Resistance Through Broadside Connectivity

August 11, 2022

The Importance of Overcoming the “Design Wall” when Working on FinFET Technology Nodes

July 20, 2022

Issues to Expect with Technology Node Shrink

July 5, 2022

The Relationship Between Device Sharing and Mask Misalignment

June 8, 2022

Identifying Dominant Interconnect Capacitance in Layout

April 15, 2022

Minimum Rule Logic in Analog Layout – Reducing Latch-up Immunity

March 10, 2022

Shorting Source to Bulk – Adding Risk to Silicon?

November 30, 2021

The Impact of Device Folding on Drain Resistance – Copy

November 19, 2021

Layout Design Cycle Times and FinFET nodes

November 18, 2021