IC Mask Design are Hosting a Free Webinar June 14th @ 4pm GMT

Webinar Power (Source) Aware Floorplan – Wed, Jun 14th  2023 4:00 PM – 5:00 PM GMT
This webinar looks at the challenges of one of the main tasks a layout engineer has i.e., making a floorplan:
The Challenges:
Making a floorplan is one of the main tasks that a layout engineer has, the implementation of the floorplan will directly affect different variables:
• Area
• Matching of devices
• Density of base layers
Although these are the main and more tangible variants that the floorplan affects, there are some others that will affect the quality and efficiency of the physical implementation of the circuit:
• Power Structure
• Routing area
• Schedule
With the “Power Aware Floor planning” methodology we will be able to have a good understanding of our power structure from the beginning for both Analog and Digital Blocks.
In the case of only digital Blocks, with this methodology, an Engineer can make good quality layout, fast, easy, and even save area compared to circuits provided by the foundries.
Speaker: IC Mask Design Technical Lead, Jorge Araiza, originates from Mexico and has over 7 years of experience working as an Analog Layout engineer, mainly in FinFET technologies. Jorge’s presentation is titled: “Power (Source) Aware Floorplan” and looks at the challenges of one of the main tasks a layout engineer has i.e., making a floorplan.
*This webinar is in partnership with IC Mask Design and SemiWiki*

Share this on...